Our Team

Our Team is building the future of technology, and so we look for the best and brightest to help us get there. We are made up of people from across the world striving to be at the forefront of innovation.

Silicon Validation Designer
Location: Fremont, CA

In this role, you will be part of a world-class IC design team responsible for the development and deployment of hardware solutions for a revolutionary computing system, which we believe can reduce the energy consumption of AI processing by two orders of magnitude over conventional digital solutions. This will completely disrupt the AI IoT landscape. It is based on our unique computing memory device with multi-bit-level capacity per cell, which is nonvolatile with excellent retention and endurance. We offer very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, daycare subsidy, and other perks.

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Responsibilities:

•  Testing and silicon debug, including writing the necessary testing code, testing platform setup, and silicon screening and debugging. Contribute to testing methodology and setup including probe card, packaged chip, and PCB testing.

• Analysis of signal integrity, noise, power, and other design issues. Work with the design team to verify circuit features and debug issues

• Help with product demo setup and running different demo benchmark/showroom projects as needed

Requirements:

• MS or PhD in Electrical Engineering or computer engineering

• Working knowledge of testing instruments such as oscilloscope, signal generator

• Working knowledge of microcontrollers (Arduino, Raspberry Pi) and/or FPGA (Xilinx or Intel)

• Scripting in C/C++, Python, Perl

• Ability to drive drivers for embedded systems in C

• Ability to work in a startup environment and to work both independently and as a team player

Experience in one or more of the following areas considered a strong plus:

• Working knowledge of data converter systems (DAC, ADC)

• Working knowledge of analog circuits (OpAmps, bandgap, temperature sensors)

• Working knowledge of RISC-V CPUs

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Multiple job openings including Engineer, Senior Engineer, Staff Engineer, Senior Staff Engineer,

Principal Engineer, Senior Principal Engineer, etc. position levels are determined by background and experience.

IC Design Engineer - Entry Level
Location: Singapore

This position is for a new or recent college graduate with a bachelor or master’s degree in electrical or Electronics Engineering. The candidate should be eager to learn and practice the discipline of microchip design and must bring strong technical fundamentals and knowledge of circuit design theory. This rigorous engineering discipline requires technical depth, flexibility, perseverance, and a passion for solving complex and difficult problems.

In this role you will be part of a world-class IC design team responsible for the development and deployment of software solutions for a revolutionary computing system, which will reduce the energy consumption of AI processing by two orders of magnitude over conventional digital solutions. This will completely disrupt the AI IoT landscape. It is based on our unique computing memory device with multi-bit-level capacity per cell, which is nonvolatile with excellent retention and endurance. We offer a very competitive compensation, commensurate with experience, and a full benefits package including insurance, paid time off, and more.

​

Requirements:

• MS or BS in Electrical Engineering, Electronics Engineering, or Physics with emphasis on circuit design including analog, digital, and mixed-signal design 

• Knowledge of the IC development flow in advanced CMOS processes including design, layout, and tape-out

• Knowledge of the basic theories of digital or analog circuit design

• Ability to create innovative designs and circuit solutions to meet customer requirements

• Ability to work in a startup environment, and to work both independently and as a team player as circumstances indicate

Experience in one or more of the following areas considered a strong plus:

• Previous tape-out experience in industry leading technology nodes

• Familiarity with industry standard IC design CAD tools such as Cadence, Synopsys, or others

• Experience with memory technologies, especially emerging non-volatile memory technologies

ASIC RTL/SoC Design Engineer
Location: Fremont, CA

In this team you be part of a world-leading IC design team responsible for the development and deployment of hardware solutions for a revolutionary computing system, which we believe can bring up the energy efficiency by another two orders of magnitude, and completely changes the AI IoT industry. It is based on our unique computing memory device, which has SoTA bit-level per cell, nonvolatile, excellent retention, and endurance. We offer a very competitive compensation and benefits package (including medical, unlimited PTO, and 401k) that commensurate with experience.

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Requirements:

• MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design

• Experience with Verilog and system Verilog

• Experience with VCS, and UVM design verification tools.

• Experience with pre-layout simulation and post-layout simulation

• Understanding of the design flow. Ability to work with the backend team

• Familiarity with AMBA APB AXI Protocol

• Familiarity with RISC/Arm or other core architectures

• Ability to create innovative architecture and solutions to customer requirements

• Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.

Experience in one or more of the following areas considered a strong plus:

• FPGA/ASIC design of image processing systems

• Working knowledge of SoC architecture such as CPU, GPU or accelerators

• Familiarity with: UVM, place-and-route, STA, EM/IR/Power

Multiple job openings including Engineer, Senior Engineer, Staff Engineer, Senior Staff Engineer,

Principal Engineer, Senior Principal Engineer, etc. position levels are determined by background and experience.

ASIC/SoC Design Verification Engineer
Location: Fremont, CA

In this role, you will be part of a world-class IC design team responsible for defining and developing a revolutionary computing system, which we believe can reduce the energy consumption of AI processing by more than two orders of magnitude over conventional digital solutions. This will completely disrupt the AI IoT landscape. It is based on our unique computing memory technologies with multi-bit-level capacity per cell, which is nonvolatile with excellent retention and endurance.

We offer a very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, daycare subsidy, and other perks.

​

Responsibilities:

•  Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification.

• Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance.

• Develop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levels.

•  Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out.

• Work with design engineers to debug and identify root causes of simulation failure.

• Support test engineers for post-silicon validation.

• Mentor and coach team members and junior engineers. Drive verification efficiency.

Requirements:

• MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree.

• In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology.

• Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and testcases development for function/performance verification.

• Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding.

• Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core.

• Experience in verifying designs at both of RTL level and post-P&R gate level.

• Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team

Experience in one or more of the following areas considered a strong plus:

• Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators

• Experience in verifying mix-signal design and interface of digital and analog.

• Experience of design verification for highspeed IO such as PCIE and DDR.

​

Multiple job openings including Engineer, Senior Engineer, Staff Engineer, Senior Staff Engineer,

Principal Engineer, Senior Principal Engineer, etc. position levels are determined by background and experience.

Analog/Mixed-Signal IC Designer - Entry Level
Location: Singapore

This position is for a new or recent college graduate with a bachelor or master’s degree in electrical or Electronics Engineering. The candidate should be eager to learn and practice the discipline of microchip design and must bring strong technical fundamentals and knowledge of circuit design theory including analog, and mixed-signal. This rigorous engineering discipline requires technical depth, flexibility, perseverance, and a passion for solving complex and difficult problems.

In this role you will be part of a world-class IC design team responsible for the development and deployment of software solutions for a revolutionary computing system, which will reduce the energy consumption of AI processing by two orders of magnitude over conventional digital solutions. This will completely disrupt the AI IoT landscape. It is based on our unique computing memory device with multi-bit-level capacity per cell, which is nonvolatile with excellent retention and endurance. We offer a very competitive compensation, commensurate with experience, and a full benefits package including insurance, paid time off, and more.

​

Requirements:

• MS or BS in Electrical Engineering, Electronics Engineering, or Physics with emphasis on CMOS analog/mixed-signal integrated circuit design

• Knowledge of the IC development flow in advanced CMOS processes including design, layout, and tape-out

• Strong knowledge in analog/mixed-signal circuits such as Op-Amp, bandgap, regulator, data converter, etc.

• Familiar with common EDA environments, and design/simulation/layout CAD tools (e.g., Synopsys, Cadence, Mentor Graphics etc.)

• Ability to work in a startup environment, and to work both independently and as a team player as circumstances indicate

Experience in one or more of the following areas considered a strong plus:

• Hands-on experience and in-depth knowledge in CMOS low-power design and techniques

•  Hands-on experience with DAC and ADC design

• Experience with memories, especially emerging non-volatile memory

ASIC RTL Design Engineer
Location: Singapore

In this role you will be part of a world-class IC design team responsible for the development and deployment of software solutions for a revolutionary computing system, which will reduce the energy consumption of AI processing by two orders of magnitude over conventional digital solutions. This will completely disrupt the AI IoT landscape. It is based on our unique computing memory device with multi-bit-level capacity per cell, which is nonvolatile with excellent retention and endurance. We offer a very competitive compensation, commensurate with experience, and a full benefits package including insurance, paid time off, and more.

​

Responsibilities:

• RTL design, simulation and verification for TetraMem ASIC / SoC products

• IP integration and validation

• Understand internal and external requirements, PPA study, RTL coding, implementation and work with backend team

• Develop reusable internal IPs for AI and/or in-memory computing products

• Support Post-Si testing and validation

• Mentor and coach junior engineers

Requirements:

• MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design

• Experience with Verilog and system Verilog

• Experience with VCS, Verdi or other industry standard tools

• Experience with pre-layout simulation and post-layout simulation

• Understanding of the design flow. Ability to work with the backend team

• Familiarity with AMBA APB AXI Protocol

• Familiarity with RISC/Arm or other core architectures

• Ability to create innovative architecture and solutions to customer requirements

• Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.

Experience in one or more of the following areas considered a strong plus:

• FPGA/ASIC design of image processing systems

• Working knowledge of SoC architecture such as CPU, GPU or accelerators

• Familiarity with: UVM, place-and-route, STA, EM/IR/Power

Multiple job openings including Engineer, Senior Engineer, Staff Engineer, Senior Staff Engineer,

Principal Engineer, Senior Principal Engineer, etc. position levels are determined by background and experience.

​

To apply, send us an email at hr@tetramem.com

ASIC Design Verification Engineer
Location: Singapore

In this role you will be part of a world-class IC design team responsible for the development and deployment of software solutions for a revolutionary computing system, which will reduce the energy consumption of AI processing by two orders of magnitude over conventional digital solutions. This will completely disrupt the AI IoT landscape. It is based on our unique computing memory device with multi-bit-level capacity per cell, which is nonvolatile with excellent retention and endurance. We offer a very competitive compensation, commensurate with experience, and a full benefits package including insurance, paid time off, and more.

​

Responsibilities:

• Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification

• Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance

• Develop reusable testbench, constrained-random/directed test cases, and verification associated behavioral modules for both block levels and system levels.

• Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out

• Work with design engineers to debug and identify root causes of simulation failure

• Support test engineers for post-silicon validation

• Mentor and coach junior engineers. Drive verification efficiency

Requirements:

• MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree

• In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology

• Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and test cases development for function/performance verification

• Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding

• Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core

• Experience in verifying designs at both RTL level and post-P&R gate level

• Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team

Experience in one or more of the following areas considered a strong plus:

• Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators

• Experience in verifying mix-signal design and interface of digital and analog

• Experience of design verification for high-speed IO such as PCIE and DDR

Multiple job openings including Engineer, Senior Engineer, Staff Engineer, Senior Staff Engineer,

Principal Engineer, Senior Principal Engineer, etc. position levels are determined by background and experience.

​

To apply, send us an email at hr@tetramem.com

ASIC Physical Design Engineer
Location: Singapore

In this role you will be part of a world-class IC design team responsible for the development and deployment of software solutions for a revolutionary computing system, which will reduce the energy consumption of AI processing by two orders of magnitude over conventional digital solutions. This will completely disrupt the AI IoT landscape. It is based on our unique computing memory device with multi-bit-level capacity per cell, which is nonvolatile with excellent retention and endurance. We offer a very competitive compensation, commensurate with experience, and a full benefits package including insurance, paid time off, and more.

​

Responsibilities:

• Collaborate with front-end design team to understand chip PPA requirement and lead physical design methodology

• Netlist to GDS including plate-and-route, clock tree optimization, timing, and ECO

• Develop and maintain automation flow for physical design

• Deliver physical design under PPA and schedule targets

• Resolve design bugs with frontend team and improve performance and power efficiency

• Support Post-Si testing and validation

• Mentor and coach junior engineers

Requirements:

• MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on digital design or physical design

• Experience with P&R, floor planning, clock tree, physical verification, timing

• Experience with sign-off flow including physical verification (DRC, LVS) and analysis flows (noise, EM, IR, UPF)

• Experience with LEC or other logic equivalent methodology

• Familiarity with RISC/Arm or other core architectures

• Ability to create innovative architecture and solutions to customer requirements

• Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team

Experience in one or more of the following areas considered a strong plus:

• Experience with RISC-V architecture

• Working knowledge of SoC architectures including CPU, GPU or accelerators

Multiple job openings including Engineer, Senior Engineer, Staff Engineer, Senior Staff Engineer,

Principal Engineer, Senior Principal Engineer, etc. position levels are determined by background and experience.

​

To apply, send us an email at hr@tetramem.com

Compiler/ML Software Engineer
Location: Fremont, CA

In this role, you will be part of a world-class IC design team responsible for the development and deployment of hardware solutions for a revolutionary computing system, which we believe can reduce the energy consumption of AI processing by two orders of magnitude over conventional digital solutions. This will completely disrupt the AI IoT landscape. It is based on our unique computing memory device with multi-bit-level capacity per cell, which is nonvolatile with excellent retention and endurance. We offer very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, daycare subsidy, and other perks.

Responsibilities:

• Develop compiler toolchain to translate deep learning models to revolutionary new hardware

• Innovative in ways to optimize the speed and efficiency of ML model inference

• Collaborate with machine learning and hardware teams

• Senior candidates will lead and mentor in a growing team

Requirements:

• MS or PhD in Computer Engineering/CS/EE

• 5+ years industry experience as a compiler engineer or developer

• Experience developing compilers for GPU, dataflow compilers, or ML compilers

• Startup mindset/experience

Experience in one or more of the following areas considered a strong plus:

• Experience with ML model compression techniques, such as quantization or pruning

• Experience providing technical leadership and/or guidance to other engineers

• Knowledge of popular CPU/GPU compilers such as GCC, Clang

• Knowledge of ML compilers such as Glow, TVM, MLIR, or XLA

• Experience with LLVM and other open-source compiler libraries and tools

• Publications on compilation of ML or dataflow programs for HW acceleration

Multiple job openings including Engineer, Senior Engineer, Staff Engineer, Senior Staff Engineer,

Principal Engineer, Senior Principal Engineer, etc. position levels are determined by background and experience.

​

To apply, send us an email at hr@tetramem.com

ML Model Software Engineer
Location: Fremont, CA

In this role, you will be part of a world-class IC design team responsible for the development and deployment of hardware solutions for a revolutionary computing system, which we believe can reduce the energy consumption of AI processing by two orders of magnitude over conventional digital solutions. This will completely disrupt the AI IoT landscape. It is based on our unique computing memory device with multi-bit-level capacity per cell, which is nonvolatile with excellent retention and endurance. We offer very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, daycare subsidy, and other perks.

​

Responsibilities:

• Develop innovative techniques for model compression

• Optimize neural network architectures to leverage our revolutionary new hardware design

• Implement, train, and improve ML models

• Senior candidates will lead and mentor in a growing team

Requirements:

• MS or PhD with published research work in ML model optimization, post-training quantization, consideration of different datasets and different constraints (bit-accuracy, model size, latency and so on).

• Experience with popular machine learning frameworks, such as PyTorch and TensorFlow 

• Startup mindset/experience

Experience in one or more of the following areas considered a strong plus:

• Experience with popular light-weight ML models on edge inference

• Hands-on experiences with deploying/evaluating ML models on resource/power-limited computing platforms.  

• Experience providing technical leadership and/or guidance to other engineers

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Multiple job openings including Engineer, Senior Engineer, Staff Engineer, Senior Staff Engineer,

Principal Engineer, Senior Principal Engineer, etc. position levels are determined by background and experience.

​

To apply, send us an email at hr@tetramem.com

SDK Development Engineer
Location: Fremont, CA

In this role, you will be part of a world-class IC design team responsible for the development and deployment of hardware solutions for a revolutionary computing system, which we believe can reduce the energy consumption of AI processing by two orders of magnitude over conventional digital solutions. This will completely disrupt the AI IoT landscape. It is based on our unique computing memory device with multi-bit-level capacity per cell, which is nonvolatile with excellent retention and endurance. We offer very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, daycare subsidy, and other perks.

​

Responsibilities:

• Develop SDK and libraries for embedded platforms

• Work within an agile organization

• Collaborate with hardware and ML teams

• Senior candidates will lead and mentor a growing team

Requirements:

• BS or MS in Computer Engineering/Computer Science/Electrical Engineering

• 5+ years of commercial HW development experience

• Embedded software development in Python and C/C++

• SDK development for resource/power-limited computing platforms (embedded or mobile).  

• Startup mindset/experience

Experience in one or more of the following areas is considered a strong plus:

• Providing technical leadership and/or guidance to other engineers

• Embedded software development on virtual platform/FPGA emulator

• Machine learning and/or ultra-low power applications

• API Design

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Multiple job openings including Engineer, Senior Engineer, Staff Engineer, Senior Staff Engineer,

Principal Engineer, Senior Principal Engineer, etc. position levels are determined by background and experience.

​

To apply, send us an email at hr@tetramem.com