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Careers

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Our Team

Our Team is building the future of technology, and so we look for the best and brightest to help us get there. We are made up of people from across the world striving to be at the forefront of innovation.

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Current Positions

IC Design Engineer - Entry Level

Location: Singapore

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This position is for a new or recent college graduate with a bachelor or master’s degree in electrical or Electronics Engineering. The candidate should be eager to learn and practice the discipline of microchip design and must bring strong technical fundamentals and knowledge of circuit design theory. This rigorous engineering discipline requires technical depth, flexibility, perseverance, and a passion for solving complex and difficult problems.

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Responsibilities: 

  • Work with Senior Engineers to understand design requirements and specifications

  • Help with analog, mixed-signal and digital IC design

  • Participate in RTL coding and verification for digital ICs

  • Help with design verification work

  • Perform circuit simulations and analysis using tools such as Cadence, Synopsys and Mentor Graphics

  • Support layout engineers with floor planning

  • Analyze and debug silicon failures and come up with design improvements

  • Contribute to the development of design methodologies to improve design efficiency

  • Design work and test plan documentation

  • Collaborate with cross functional teams to ensure successful tape-out

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Requirements:

  • MS or BS in Electrical Engineering, Electronics Engineering, or Physics with emphasis on circuit design including analog, digital, and mixed-signal design 

  • Knowledge of the IC development flow in advanced CMOS processes including design, layout, and tape-out

  • Knowledge of the basic theories of digital or analog circuit design

  • Ability to create innovative designs and circuit solutions to meet customer requirements

  • Ability to work in a startup environment, and to work both independently and as a team player as circumstances indicate

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Experience in one or more of the following areas considered a strong plus:

  • Previous tape-out experience in industry leading technology nodes

  • Familiarity with industry standard IC design CAD tools such as Cadence, Synopsys, or others

  • Experience with memory technologies, especially emerging non-volatile memory technologies

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Job Type: Full-time

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Pay Range For This Position:

SG$30 - SG$50 Per hour

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To apply, please send your resume to hrteam@tetramem.com

 

ASIC/SoC Design Verification Engineer

Location: Fremont, CA

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Responsibilities:

  • Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification

  • Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance

  • Develop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levels

  • Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out

  • Work with design engineers to debug and identify root causes of simulation failure

  • Support test engineers for post-silicon validation

  • Mentor and coach team members and junior engineers. Drive verification efficiency

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Requirements:

  • MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree

  • In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology

  • Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and testcases development for function/performance verification

  • Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding

  • Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core

  • Experience in verifying designs at both of RTL level and post-P&R gate level

  • Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team

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Experience in one or more of the following areas considered a strong plus:

  • Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators

  • Experience in verifying mix-signal design and interface of digital and analog

  • Experience of design verification for highspeed IO such as PCIE and DDR

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Job Type: Full-time

 

Pay Range For This Position:

$110,000 - $300,000

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All of our openings span various levels, ranging from Engineer to Senior Principal Engineer, including corresponding management roles. Our job levels and salaries are clearly structured, reflecting the candidates' backgrounds and experience to ensure a fair and transparent progression in their careers.

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To apply, please send your resume to hrteam@tetramem.com

ASIC RTL Design Engineer

Location: ​Fremont, CA, USA & Singapore

 

Responsibilities:

  • Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs

  • Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility

  • Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs

  • Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout

  • Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications

  • Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product

  • Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth

  • Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability

  • Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency

  • Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery

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Requirements:

  • MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design

  • Experience with Verilog and system Verilog

  • Experience with VCS, Verdi or other industry standard tools

  • Experience with pre-layout simulation and post-layout simulation

  • Understanding of the design flow. Ability to work with the backend team

  • Familiarity with AMBA APB AXI Protocol

  • Familiarity with RISC/Arm or other core architectures

  • Ability to create innovative architecture and solutions to customer requirements

  • Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.

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Experience in one or more of the following areas considered a strong plus:

  • FPGA/ASIC design of image processing systems

  • Working knowledge of SoC architecture such as CPU, GPU or accelerators

  • Familiarity with: UVM, place-and-route, STA, EM/IR/Power

 

Job Type: Full-time

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Pay Range For This Position:

Singapore: SG$80,000 - SG$180,000

Fremont, CA, USA: $110,000 - $300,000

 

All of our openings span various levels, ranging from Engineer to Senior Principal Engineer, including corresponding management roles. Our job levels and salaries are clearly structured, reflecting the candidates' backgrounds and experience to ensure a fair and transparent progression in their careers.

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To apply, please send your resume to hrteam@tetramem.com

ASIC Design Verification Engineer

Location: Singapore

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Responsibilities:

  • Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification

  • Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance

  • Develop reusable testbench, constrained-random/directed test cases, and verification associated behavioral modules for both block levels and system levels

  • Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out

  • Work with design engineers to debug and identify root causes of simulation failure

  • Support test engineers for post-silicon validation

  • Mentor and coach junior engineers. Drive verification efficiency

​

Requirements:

  • MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree

  • In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology

  • Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and test cases development for function/performance verification

  • Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding

  • Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core

  • Experience in verifying designs at both RTL level and post-P&R gate level

  • Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team

​

Experience in one or more of the following areas considered a strong plus:

  • Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators

  • Experience in verifying mix-signal design and interface of digital and analog

  • Experience of design verification for high-speed IO such as PCIE and DDR

​

Job Type: Full-time

​

Pay Range For This Position:

SG$80,000 - SG$180,000

 

All of our openings span various levels, ranging from Engineer to Senior Principal Engineer, including corresponding management roles. Our job levels and salaries are clearly structured, reflecting the candidates' backgrounds and experience to ensure a fair and transparent progression in their careers.

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To apply, please send your resume to hrteam@tetramem.com

Analog/Mixed-Signal IC Verification Engineer

Location: Fremont, CA

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Responsibilities:

  • Develop and implement mixed-signal verification and coverage plans for complex IC designs based on design architecture and specifications

  • Design and develop verification testbenches using industry-standard verification languages and methodologies

  • Write and execute test cases to verify mixed-signal circuits for functionality, performance, and reliability

  • Review and analyze verification results, and provide feedback to design teams

  • Collaborate with design and layout teams to identify and resolve design issues

  • Develop new verification methodologies, tools, and techniques, ensuring scalability and portability

  • Sign-off mixed signal designs in preparation for tapeout

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Requirements:

  • B.S. EE and 7+ years of relevant industry experience or equivalent

  • Strong understanding of analog and mixed-signal circuit design and verification principles

  • Ability to write test plans, present results, and communicate clearly with multi-functional teams

  • Have a familiarity with verification methodologies and tools: simulators, waveform viewers, execution automation, simulation time optimization, and coverage collection

  • Have good programming skills and can write efficient programs or scripts in Perl, Python, and/or C

  • Excellent debugging, problem-solving and analytical skills

  • Strong communication and teamwork skills

  • Familiarity with analog behavioral models is a plus

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Job Type: Full-time

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Pay Range For This Position:

$110,000 - $300,000 per year

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All of our openings span various levels, ranging from Engineer to Senior Principal Engineer, including corresponding management roles. Our job levels and salaries are clearly structured, reflecting the candidates' backgrounds and experience to ensure a fair and transparent progression in their careers.

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To apply, please send your resume to hrteam@tetramem.com

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Senior Level Embedded Software Engineer

Location: Fremont, CA

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Responsibilities:​

  • Establish software systems and subsystems, including firmware, device drivers and application software

  • Collaborate with hardware engineers to define system requirements, hardware/software interfaces, and system integration strategies

  • Design and optimize chipset configurations

  • Collaborate with the software development team to implement and test LLMs on selected chipsets

  • Design and implement embedded software, device drivers, and board support packages

  • Investigate and propose project-related technologies to meet requirements

  • Create technical documentation, including Software Requirements Specifications, Design Documents, Test Summary Reports, and development notes

  • Define and execute engineering verification and acceptance criteria tests

  • Mentor junior engineers, provide technical guidance, and facilitate knowledge sharing within the team

  • Participate in code reviews, design reviews, and project planning activities

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Requirements:

  • MS with 5+ years of related experience 

  • Experience with Embedded system development or FPGA

  • Ability to work in a startup environment and work both independently and as a team player

  • Ability to provide technical leadership to other members of the engineering team

  • Track record of shipping products as an embedded software engineer

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Experience in one or more of the following areas is considered as a strong plus:

  • Experience with ML compilers such as TVM, XLA, Glow, GGML as well as compiler frameworks such as MLIR

  • Experience with the internals of ML frameworks and runtimes such as PyTorch, TF, TFLite and TFLite Micro

  • Experience with ML, work with edge light-weight AI models

  • Publications or talks in top relevant conferences on software development

  • Hands-on experience on developing compiler libraries or tools

  • Hands-on experience with driver development for ASIC/FPGA

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Job Type: Full-time

 

Pay Range for This Position:

$220,000 - $300,000 per year

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Our job openings encompass a broad range of positions, from Engineer up to Senior Principal Engineer, including relevant management positions. For the Senior Level Embedded Software Engineer role, we are looking for candidates at the staff level or above. We have a well-defined structure for job levels and salaries, designed to reflect the candidate's background and experience, ensuring a transparent and equitable career progression. 

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To apply, please send your resume to hrteam@tetramem.com

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Memory Circuit Design Engineer

Location: Fremont, CA

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Responsibilities:

  • Design memory IC projects from initial concept to the tape-out phase, ensuring a smooth and successful development process

  • Define and implement memory architectures and circuits, with a focus on optimizing speed, power efficiency, and silicon area utilization

  • Create comprehensive test plans to thoroughly evaluate memory designs, leveraging simulation tools and methodologies to validate functionality and performance

  • Identify and troubleshoot design issues, utilizing simulation and analysis to isolate problems and develop effective solutions

  • Collaborate with cross-functional teams to analyze and enhance the performance of memory designs, addressing bottlenecks and ensuring optimal operation

  • Work closely with analog and digital engineering teams to ensure seamless integration of memory designs into the overall product development, maintaining compatibility and functionality

  • Investigate and resolve design-related issues as they arise, contributing to the silicon bring-up and validation activities for memory ICs

  • Stay current with industry advancements in memory design, exploring and implementing cutting-edge techniques and technologies

  • Implement rigorous testing and validation processes to ensure memory designs meet quality and reliability standards

  • Maintain detailed documentation of memory design processes, methodologies, and findings to support team collaboration and project continuity

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Requirements:

  • MS or PhD in Electrical Engineering with emphasis on CMOS memory, digital or mixed-signal design

  • 5+ years of experience in circuit design in advanced CMOS processes (PhD experience may be considered as experience), successful tape-out experience with leading foundries

  • Experience in memory circuit design in one of: SRAM, DRAM, Flash or emerging NVM technologies

  • Strong understanding of layout design including layout dependent effects, pitch matching, and design for manufacturing

  • Familiar with common EDA environment tools, CAD tools and memory design methodology including design, simulation, layout, and verification tools (e.g. Synopsys， Cadence, Mentor Graphics etc.).

  • Ability to create innovative architecture and circuit solutions to customer requirements

  • Ability to work in startup environment and work both independently and as a team player

 

Experience in one or more of the following areas considered a strong plus:

  • Hands-on production experience with key memory blocks such as sense amplifier, charge pump, read/write assist circuit, PVT tracker, power gating etc

  • Familiar with memory controller or memory interface

  • Experience with emerging non-volatile memory

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Job Type: Full-time

 

Pay Range for This Position:

$110,000 - $300,000 per year

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All of our openings span various levels, ranging from Engineer to Senior Principal Engineer, including corresponding management roles. Our job levels and salaries are clearly structured, reflecting the candidates' backgrounds and experience to ensure a fair and transparent progression in their careers.

​

To apply, please send your resume to hrteam@tetramem.com

Head/Sr. Director of Foundry Interface and Process Integration

Location: Fremont, CA

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Responsibilities: 

  • Lead foundry process integration and efficient resource utilization

  • Define and implement strategies for fab integrating processes

  • Collaborate with R&D for product innovation and quality

  • Ensure compliance with regulatory and quality standards

  • Budget and resource management for cost-effective operations

  • Partner selection and contract negotiation with foundry providers

  • Continuous assessment and optimization of foundry processes

  • Quality assurance implementation for high product standards

  • Mentorship and professional development of team members

  • Stay updated with the latest smart sensor advancements

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Requirements:

  • ​Bachelor's or Master's degree in Engineering, Electrical Engineering, or related field (Advanced degree preferred)

  • Proven experience in foundry integration, process integration, and smart sensor technology

  • Strong leadership and team management skills

  • Excellent communication and problem-solving abilities

  • Knowledge of industry regulations and compliance standards

  • Smart Sensor and CMOS Image sensor experience preferred

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Job Type: Full-time

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Pay Range for This Position:

$200,000 - $300,000 per year

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To apply, please send your resume to hrteam@tetramem.com

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